Skip to navigation Skip to content

Intona products are engineered and made in Germany. We ship worldwide daily.

Intellectual Property

IP Core Modules for FPGA use

Intona offers sophisticated modules for audio digital signal processing and multimedia data transmission purposes. The IP cores have been successfully deployed in real devices using Xilinx Spartan, Artix and Kintex FPGA. Some modules where also deployed on Lattice ECP5 using the Yosys/Nextpnr open source toolchain. All modules are written in Verilog.

Asynchronous Sample Rate Converter

Ultra-low Latency, Small Footprint

  • 32 audio channels per stride
  • 24 bit fixed point
  • 30 to 230 kHz input sample rate
  • 30 to 230 kHz output sample rate
  • < -135 dB THD+N typical
  • qualifies as replacement for CS8422
  • industry-wide lowest latency (0.3 ms easily possible)
  • smallest footprint: 32 channels in XC6SLX4, 96 in SLX9, 224 in SLX16
  • occupied Spartan 6 slices: 430 for 32 channels, 510 for 64 channels
  • User Guide: HTML PDF

Lattice Ladder IIR Filters

Lowest Distortion, Analog Feeling

  • 32, 40, 48 or 64 bit floating point
  • eight channels à 20 filters (32 on 7-series FPGAs) or
  • sixteen channels à 10 filters (16 on 7-series FPGAs)
  • chainable
  • filter types (excerpt): parametric eq, shelving eq, low/high/all-pass filters
  • less recursion than direct form (although more complex)
  • separate coefficients for Q and Fc
  • precise feedback quantization: excellent bit utilization even at low signal frequencies and high sample rates
  • very low distortion and analogue sound
  • four modules (= 640 filters) fit easily in XC3S500E
  • simple bus interface for coefficient loading
  • coefficient calculation LUT based or using separate MCU (C code provided)
  • highest stability even in modulated systems like VCF
  • lowest quantization noise industrial-wide

True-RMS Compressor/Limiter

plus zero-delay Peak Limiter

  • 32, 40, 48 or 64 bit floating point
  • parameters: threshold (dBFS), attack (ms), release (ms), knee (dB), crest (dB)
  • sophisticated peak limiter with guaranteed voltage protection
  • sixteen channels with a latency of only one sample at 96 kHz
  • simple bus interface for coefficient loading
  • coefficient calculation using separate MCU (C code provided)
  • ideal supplement to the Lattice Ladder Core

I2S/TDM Transceiver

Very Small Footprint

  • save 90% of flip-flops compared to conventional serial/parallel conversion

Ethernet Transceiver MAC

Low Latency Media Transport

  • connects UDP packets directly to FPGA resources
  • deterministic latency, no external buffers needed
  • Linux kernel driver available

Gigabit Ethernet Transceiver MAC

Small Footprint

  • PTP hardware time stamps
  • AVB-Ready
  • Linux kernel driver available

Gigabit AVB Endpoint

Audio Video Bridging

  • up to 420 audio channels
  • clock recovery or low-latency ASRC
  • requires MCU (Microblaze, ARM, Risc-V) for house keeping
  • Linux-based control software

Precision lin/log functions

log10(x) and 10x

  • 32 bit floating point
  • ultra small footprint
  • 40 million operations per second at 120 MHz on Spartan
  • 80 million operations per second at 240 MHz on 7-series
  • standard deviation less than 0.01dB

AES67 audio streaming endpoint

Project name: AVALOT

  • receive streams with any number of channels and pick 1..4 for play out
  • optional transmission of a stream
  • clock recovery using internal PLL
  • optional upsampling to 96k
  • JSON-based API over UDP and serial UART
  • includes a compact RISC-V soft MCU
  • reference implementation for ECP5 using Yosys/Nextpnr

JSON Parser

A simple JSON parser. Written in C, suitable for embedded use. In particular, it's small and compact, yet fully featured and easy to use.

It also supports a minimum of error reporting. The main focus is on correctness, small code size, low dependencies, and ease of use.

The JSON parser is available as open-source software on GitHub.

.
.