Is there any customization possible, for example using a better oscillator?

What would you expect by using a "better" oscillator?

We measured 12.5ps of RMS jitter on the USB packet clock. A more or less jittery oscillator would not make any difference on this, because of the very low tuned lp-filter in the transceiver's PLL.

We use four clocks in our design, all shifted slightly in phase and affected from natural spread spectrum of the isolator chips and other sources. This really helps to bring EMI down and to spread current peaks – e.g. to lower the packet noise.
If we would tune everything inside to least jitter, this would rise packet noise and also EMI radiation.

One need to distinguish between

• sample clock in an ADC or DAC: low jitter is the most important, because only the right sample at the right time is the right sample
• transmission clock of a serial system: BER (bit error rate) or eye mask to be specified
• clock passing integrated logic: setup and hold times to be met

We decided to go for low noise, so spreading clocks and accepting inter-logic-skew was the way to go. Further, clever design of return currents and also a good and low impedance decoupling network of the power supplies are by far more important to meet your needs than looking for the oscillator.